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| author |   Richard Fitzgerald <rf@opensource.cirrus.com> | 2024-12-16 11:27:20 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2024-12-16 12:31:15 +0000 |
| commit | bc7bd5c335030858216581e7a591d02ebfdb53e7 (patch) | |
| tree | 3bf4f3a9c9118fccc2d07d55a1da6ba8809eafb2 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ASoC: Intel: tgl-match: Add entries for CS35L56 on CDB35L56-EIGHT-C (diff) | |
| download | wireguard-linux-bc7bd5c335030858216581e7a591d02ebfdb53e7.tar.xz wireguard-linux-bc7bd5c335030858216581e7a591d02ebfdb53e7.zip | |
ASoC: Intel: mtl-match: Add CDB35L56-EIGHT-C with aggregated speakers
This adds a match for the CDB35L56-EIGHT-C board with SmartCodec and
SmartAmp speakers aggregated.
The configuration is:
SDW0: CS35L56 x2 (SmartAmp) using OUT1 and OUT2
SDW1: CS35L56 x2 (SmartAmp) using OUT7 and OUT8
SDW3: CS42L43 (SmartJack, SmartMic, SmartAmp)
CS35L56 and CS42L43 Speaker playback is aggregated across all 3 buses.
The device addresses and reset arrangements of the EIGHT-C board are
quirky hence the use of non-contiguous outputs OUT1,2,7,8.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://patch.msgid.link/20241216032721.131227-3-yung-chuan.liao@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions