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| author |   chunhui dai <chunhui.dai@mediatek.com> | 2019-02-25 10:09:10 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2019-02-25 09:19:33 -0800 |
| commit | d3174bc836d5aadc871f74ed496694c5ea27b104 (patch) | |
| tree | 750508a5799b4feb87b03fd40c6703680cbf3cfe /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: mediatek: add MUX_GATE_FLAGS_2 (diff) | |
| download | wireguard-linux-d3174bc836d5aadc871f74ed496694c5ea27b104.tar.xz wireguard-linux-d3174bc836d5aadc871f74ed496694c5ea27b104.zip | |
clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
The MUX clock of dpi1_sel should select the closet clock for itself.
We could add this flag to enable this function of MUX in CCF.
Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
Signed-off-by: wangyan wang <wangyan.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions