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| author |   Jiri Pirko <jiri@nvidia.com> | 2024-10-30 09:11:57 +0100 |
|---|---|---|
| committer |   Jakub Kicinski <kuba@kernel.org> | 2024-11-03 08:39:07 -0800 |
| commit | e2017f27b6f888fb4ebc5c9a6d984bbf2f8b99ff (patch) | |
| tree | 0e2e4e44c21a6e494893e858ad22ebc0b47c0355 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dpll: add clock quality level attribute and op (diff) | |
| download | wireguard-linux-e2017f27b6f888fb4ebc5c9a6d984bbf2f8b99ff.tar.xz wireguard-linux-e2017f27b6f888fb4ebc5c9a6d984bbf2f8b99ff.zip | |
net/mlx5: DPLL, Add clock quality level op implementation
Use MSECQ register to query clock quality from firmware. Implement the
dpll op and fill-up the quality level value properly.
Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: Jiri Pirko <jiri@nvidia.com>
Link: https://patch.msgid.link/20241030081157.966604-3-jiri@resnulli.us
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions