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| author |   Kedareswara rao Appana <appana.durga.rao@xilinx.com> | 2016-05-13 12:33:29 +0530 |
|---|---|---|
| committer |   Vinod Koul <vinod.koul@intel.com> | 2016-05-13 15:00:18 +0530 |
| commit | fb2366675ec2221241bea83dc4ec57ed33ce3dcd (patch) | |
| tree | 6c047434a86bc399c70cb00ff2950bd18b1de208 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dmaengine: vdma: Add Support for Xilinx AXI Central Direct Memory Access Engine (diff) | |
| download | wireguard-linux-fb2366675ec2221241bea83dc4ec57ed33ce3dcd.tar.xz wireguard-linux-fb2366675ec2221241bea83dc4ec57ed33ce3dcd.zip | |
dmaengine: vdma: Add config structure to differentiate dmas
This patch adds config structure in the driver to differentiate
AXI DMA's and to add more features(clock support etc..) to these DMA's.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions