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| author |   Nick Kossifidis <mick@ics.forth.gr> | 2021-04-19 03:55:36 +0300 |
|---|---|---|
| committer |   Palmer Dabbelt <palmerdabbelt@google.com> | 2021-04-26 08:25:21 -0700 |
| commit | fba8a8674f68a0628abae470dfcfbcb4a0d7a79e (patch) | |
| tree | e062971122d415840b630031d7ee59f15f2095f7 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | RISC-V: Add EM_RISCV to kexec UAPI header (diff) | |
| download | wireguard-linux-fba8a8674f68a0628abae470dfcfbcb4a0d7a79e.tar.xz wireguard-linux-fba8a8674f68a0628abae470dfcfbcb4a0d7a79e.zip | |
RISC-V: Add kexec support
This patch adds support for kexec on RISC-V. On SMP systems it depends
on HOTPLUG_CPU in order to be able to bring up all harts after kexec.
It also needs a recent OpenSBI version that supports the HSM extension.
I tested it on riscv64 QEMU on both an smp and a non-smp system.
Signed-off-by: Nick Kossifidis <mick@ics.forth.gr>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to '')
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