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| author |   Alvin Lee <alvin.lee2@amd.com> | 2023-12-01 06:25:07 -0700 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2023-12-06 15:59:17 -0500 |
| commit | fec05adc40c25a028c9dfa9d540f800a2d433f80 (patch) | |
| tree | 5ae3e9616646bb755a4ee89d3a58015493c23be1 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amdgpu: disable MCBP by default (diff) | |
| download | wireguard-linux-fec05adc40c25a028c9dfa9d540f800a2d433f80.tar.xz wireguard-linux-fec05adc40c25a028c9dfa9d540f800a2d433f80.zip | |
drm/amd/display: Use channel_width = 2 for vram table 3.0
VBIOS has suggested to use channel_width=2 for any ASIC that uses vram
info 3.0. This is because channel_width in the vram table no longer
represents the memory width
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Samson Tam <samson.tam@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions