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author | 2025-03-01 09:27:12 +0530 | |
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committer | 2025-03-01 15:07:19 +0100 | |
commit | 35b2b3328c2e02b544f49d010170fe981f20ff11 (patch) | |
tree | a9097f0acd773fcd72de0182f0c6f650c2c48ae3 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | dt-bindings: clock: add Exynos2200 SoC (diff) | |
download | wireguard-linux-35b2b3328c2e02b544f49d010170fe981f20ff11.tar.xz wireguard-linux-35b2b3328c2e02b544f49d010170fe981f20ff11.zip |
dt-bindings: clock: add clock definitions and documentation for exynos7870 CMU
Add unique identifiers for exynos7870 clocks for every bank. It adds all
clocks of CMU_MIF, CMU_DISPAUD, CMU_G3D, CMU_ISP, CMU_MFCMSCL, and
CMU_PERI. Document the devicetree bindings as well.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250301-exynos7870-pmu-clocks-v5-1-715b646d5206@disroot.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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