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| author |   Sander Vanheule <sander@svanheule.net> | 2025-01-19 19:34:22 +0100 |
|---|---|---|
| committer |   Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2025-02-21 15:10:17 +0100 |
| commit | 4b7785dd43b8eeae3534da4a13922a361eace8ff (patch) | |
| tree | fead70f21c2c3bae28f55827c38b6f2ba88ac471 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | mips: dts: realtek: Correct uart interrupt-parent (diff) | |
| download | wireguard-linux-4b7785dd43b8eeae3534da4a13922a361eace8ff.tar.xz wireguard-linux-4b7785dd43b8eeae3534da4a13922a361eace8ff.zip | |
mips: dts: realtek: Replace uart clock property
Add a fixed clock to define the clock frequency of the Lexra bus and use
this for the two uart nodes instead of a separate clock-frequency
property.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions