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| author |   Alex Deucher <alexander.deucher@amd.com> | 2025-01-06 12:19:11 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-01-24 09:53:30 -0500 |
| commit | 64314e3f9c11578b28f145fc9a4b37ca1196fafd (patch) | |
| tree | 972508d4b9df197a7eed32a487f326af6ba734b1 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amdgpu: cache gpu pcie link width (diff) | |
| download | wireguard-linux-64314e3f9c11578b28f145fc9a4b37ca1196fafd.tar.xz wireguard-linux-64314e3f9c11578b28f145fc9a4b37ca1196fafd.zip | |
drm/amdgpu: fix the PCIe lanes reporting in the INFO IOCTL
Combine the platform and GPU caps like we do for PCIe Gen.
This aligns properly with expectations and documentation
for the interface.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3820
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions