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author | 2025-02-23 13:55:58 +0200 | |
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committer | 2025-03-01 15:03:13 +0100 | |
commit | 6662c09c0ddf10ef97b430533bb9e2f0a8fbe471 (patch) | |
tree | 7a440e8f02ddc1f05a8e3d4a7ae7bce27d561f96 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | dt-bindings: clock: exynos990: Add CMU_PERIS block (diff) | |
download | wireguard-linux-6662c09c0ddf10ef97b430533bb9e2f0a8fbe471.tar.xz wireguard-linux-6662c09c0ddf10ef97b430533bb9e2f0a8fbe471.zip |
dt-bindings: clock: add Exynos2200 SoC
Provide dt-schema documentation for Exynos2200 SoC clock controller.
Add device tree clock binding definitions for the following CMU blocks:
- CMU_ALIVE
- CMU_CMGP
- CMU_HSI0
- CMU_PERIC0/1/2
- CMU_PERIS
- CMU_TOP
- CMU_UFS
- CMU_VTS
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250223115601.723886-2-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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