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| author |   Bard Liao <bardliao@realtek.com> | 2014-09-26 11:06:40 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2014-09-26 09:14:27 +0100 |
| commit | 66d627d554a4284dad00b2039efd18e1c129cc2f (patch) | |
| tree | f5c43d3f5ff914dba949b4d0818cc16f3a0954b1 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ASoC: rt286: Correct default value (diff) | |
| download | wireguard-linux-66d627d554a4284dad00b2039efd18e1c129cc2f.tar.xz wireguard-linux-66d627d554a4284dad00b2039efd18e1c129cc2f.zip | |
ASoC: rt286: Fix sync function
We try to write index registers into cache when we write an index
register, but we change the reg value before updating the cache.
As a result, the cache is never be updated. This patch will fix
this issue.
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions