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| author |   Markos Chandras <markos.chandras@imgtec.com> | 2014-07-18 10:51:31 +0100 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2014-09-22 13:35:52 +0200 |
| commit | 80bc94d10466c710158d5f30c43625ed9fa59e78 (patch) | |
| tree | d91cca1d045d8fccf6503747459a027114c239b3 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | MIPS: pgtable-bits: Move the CCA bits out of the core's ifdef blocks (diff) | |
| download | wireguard-linux-80bc94d10466c710158d5f30c43625ed9fa59e78.tar.xz wireguard-linux-80bc94d10466c710158d5f30c43625ed9fa59e78.zip | |
MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores
Ingenic uses the CCA:1 bit to achieve write-combine memory writes.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7401/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions