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| author |   Pratyush Yadav <p.yadav@ti.com> | 2020-10-05 21:01:26 +0530 |
|---|---|---|
| committer |   Vignesh Raghavendra <vigneshr@ti.com> | 2020-11-09 11:56:16 +0530 |
| commit | 0e30f47232ab57c685258aa91adc3a3e67bd023e (patch) | |
| tree | 81fd5cdadd13f4a44625876a76517a75bf537655 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | mtd: spi-nor: add spi_nor_controller_ops_{read_reg, write_reg, erase}() (diff) | |
| download | wireguard-linux-0e30f47232ab57c685258aa91adc3a3e67bd023e.tar.xz wireguard-linux-0e30f47232ab57c685258aa91adc3a3e67bd023e.zip | |
mtd: spi-nor: add support for DTR protocol
Double Transfer Rate (DTR) is SPI protocol in which data is transferred
on each clock edge as opposed to on each clock cycle. Make
framework-level changes to allow supporting flashes in DTR mode.
Right now, mixed DTR modes are not supported. So, for example a mode
like 4S-4D-4D will not work. All phases need to be either DTR or STR.
The xSPI spec says that "The program commands provide SPI backward
compatible commands for programming data...". So 8D-8D-8D page program
opcodes are populated with using 1S-1S-1S opcodes.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20201005153138.6437-4-p.yadav@ti.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions