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| author |   Claudiu Beznea <claudiu.beznea@microchip.com> | 2021-10-11 14:27:14 +0300 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2021-10-26 18:27:43 -0700 |
| commit | 0ef99f8202c5078a72c05af76bfaed2ea4daab19 (patch) | |
| tree | 6a2d76aaa74d430fd4bc51ac1345c491a78b1c8c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: at91: clk-master: mask mckr against layout->mask (diff) | |
| download | wireguard-linux-0ef99f8202c5078a72c05af76bfaed2ea4daab19.tar.xz wireguard-linux-0ef99f8202c5078a72c05af76bfaed2ea4daab19.zip | |
clk: at91: clk-master: fix prescaler logic
When prescaler value read from register is MASTER_PRES_MAX it means
that the input clock will be divided by 3. Fix the code to reflect
this.
Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-11-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions