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| author |   Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2018-08-30 16:56:35 +0200 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2018-09-13 09:47:56 +0200 |
| commit | 103db9b539567073de2200a8a0a725646610865d (patch) | |
| tree | c39fa1ba54d6bd8f5e4226e31d8857e1015091cc /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: renesas: r8a77990: Use CPG/MSSR and SYSC binding definitions (diff) | |
| download | wireguard-linux-103db9b539567073de2200a8a0a725646610865d.tar.xz wireguard-linux-103db9b539567073de2200a8a0a725646610865d.zip | |
arm64: dts: renesas: r8a77990: Add BRG support to SCIF2
Add the device node for the external SCIF_CLK, and describe the clock
inputs for the Baud Rate Generator for External Clock (BRG) for SCIF2,
which can increase serial clock accuracy.
The presence of the SCIF_CLK crystal and its clock frequency depend on
the actual board.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Enhance patch description]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions