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| author |   Sunil Goutham <sgoutham@cavium.com> | 2017-03-28 16:11:12 +0530 |
|---|---|---|
| committer |   Will Deacon <will.deacon@arm.com> | 2017-04-06 16:06:42 +0100 |
| commit | 125458ab3aefe9cf2f72dcfe7338dc9ad967da0b (patch) | |
| tree | e2ba9f68bdf1b410d8e2b9c1dc50f719806c5afa /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | iommu/arm-smmu: Print message when Cavium erratum 27704 was detected (diff) | |
| download | wireguard-linux-125458ab3aefe9cf2f72dcfe7338dc9ad967da0b.tar.xz wireguard-linux-125458ab3aefe9cf2f72dcfe7338dc9ad967da0b.zip | |
iommu/arm-smmu: Fix 16-bit ASID configuration
16-bit ASID should be enabled before initializing TTBR0/1,
otherwise only LSB 8-bit ASID will be considered. Hence
moving configuration of TTBCR register ahead of TTBR0/1
while initializing context bank.
Signed-off-by: Sunil Goutham <sgoutham@cavium.com>
[will: rewrote comment]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions