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| author |   Nicholas Piggin <npiggin@gmail.com> | 2017-11-07 18:53:05 +1100 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2017-11-10 21:30:44 +1100 |
| commit | 14001c60939a754717893672209160cec1e2ac18 (patch) | |
| tree | b7a6156fe646037c9d3fe940719d4355219c05ba /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge branch 'fixes' into next (diff) | |
| download | wireguard-linux-14001c60939a754717893672209160cec1e2ac18.tar.xz wireguard-linux-14001c60939a754717893672209160cec1e2ac18.zip | |
powerpc/64s/radix: Optimize TLB range flush barriers
Short range flushes issue a sequences of tlbie(l) instructions for
individual effective addresses. These do not all require individual
barrier sequences, only one covering all tlbie(l) instructions.
Commit f7327e0ba3 ("powerpc/mm/radix: Remove unnecessary ptesync")
made a similar optimization for tlbiel for PID flushing.
For tlbie, the ISA says:
The tlbsync instruction provides an ordering function for the
effects of all tlbie instructions executed by the thread executing
the tlbsync instruction, with respect to the memory barrier
created by a subsequent ptesync instruction executed by the same
thread.
Time to munmap 30 pages of memory (after mmap, touch):
local global
vanilla 10.9us 22.3us
patched 3.4us 14.4us
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions