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| author |   Krzysztof Kozlowski <krzk@kernel.org> | 2019-04-15 20:05:09 +0200 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2019-04-24 19:53:23 +0200 |
| commit | 1e440c223503c24959fcccb96c2b0e775a6b3bb9 (patch) | |
| tree | 49dbaf9919e5cbaa4535252b37121d08a73f332b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: exynos: Remove unneeded address/size cells from fixed-clock on Exynos3250 (diff) | |
| download | wireguard-linux-1e440c223503c24959fcccb96c2b0e775a6b3bb9.tar.xz wireguard-linux-1e440c223503c24959fcccb96c2b0e775a6b3bb9.zip | |
ARM: dts: exynos: Move fixed-clocks out of soc on Exynos3250
The three fixed-clocks (xusbxti, xxti and xtcxo) are inputs to the
Exynos3250 therefore they should not be inside the soc node. This also
fixes DTC W=1 warning:
arch/arm/boot/dts/exynos3250.dtsi:112.21-139.5:
Warning (simple_bus_reg): /soc/fixed-rate-clocks: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions