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| author |   Matt Roper <matthew.d.roper@intel.com> | 2021-05-11 21:21:38 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-05-12 16:56:38 -0700 |
| commit | 20fe778fde26f16fd3df28dba9fea889054380eb (patch) | |
| tree | 219e6b530efa4358d5374b719d0acfe0a74e55b3 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915: Use correct downstream caps for check Src-Ctl mode for PCON (diff) | |
| download | wireguard-linux-20fe778fde26f16fd3df28dba9fea889054380eb.tar.xz wireguard-linux-20fe778fde26f16fd3df28dba9fea889054380eb.zip | |
drm/i915/xelpd: Handle proper AUX interrupt bits
XE_LPD has new AUX interrupt bits for DDI-D and DDI-E that take the
spots that were used by TC5/TC6 on Display12 platforms.
While we're at it, let's convert the bit definitions for all TGL+ aux
bits over to the modern REG_BIT() notation.
v2:
- Maintain bit order rather than logical order. (Lucas)
- Convert surrounding code to REG_BIT() notation. (Lucas)
Bspec: 50064
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210512042144.2089071-2-matthew.d.roper@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions