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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2021-11-22 10:39:04 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-26 13:53:02 +0100 |
| commit | 217c7d1840b5377543eff84fe28409d0bd4d3433 (patch) | |
| tree | d7f96a697b724bcb9c77d40765cace12da20714b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dt-bindings: power: renesas,rcar-sysc: Document r8a779f0 SYSC bindings (diff) | |
| download | wireguard-linux-217c7d1840b5377543eff84fe28409d0bd4d3433.tar.xz wireguard-linux-217c7d1840b5377543eff84fe28409d0bd4d3433.zip | |
dt-bindings: mmc: renesas,sdhi: Rename RZ/G2L clocks
Rename the below RZ/G2L clocks to match with the clock names used in
R-Car Gen2 and later generations.
imclk->core
clk_hs->clkh
imclk2->cd
This changes will avoid using fallback for RZ/G2L high speed clock,
if "clkh" is not used in device tree and also the code changes in
driver related to this clocks.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/r/20211122103905.14439-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions