diff options
| author |   Palmer Dabbelt <palmerdabbelt@google.com> | 2021-10-21 08:22:37 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2021-10-21 08:22:37 -0700 |
| commit | 241527bb84674bd597113892ecf2c7ed4a410e00 (patch) | |
| tree | 9154f870ac860e376f8bde6fd4c85c4dda9030a9 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | riscv: dts: microchip: use vendor compatible for Cadence SD4HC (diff) | |
| parent | riscv: dts: sifive: add missing compatible for plic (diff) | |
| download | wireguard-linux-241527bb84674bd597113892ecf2c7ed4a410e00.tar.xz wireguard-linux-241527bb84674bd597113892ecf2c7ed4a410e00.zip | |
Merge tag 'riscv-sifive-dt-5.16' of git://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux into for-next
RISC-V DTS changes for v5.16
Cleanups of RISC-V SiFive and Microchip DTSes with dtschema. These are
few minor fixes to make DTSes pass the dtschema, without actual
functional effect.
* tag 'riscv-sifive-dt-5.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
riscv: dts: sifive: add missing compatible for plic
riscv: dts: microchip: add missing compatibles for clint and plic
riscv: dts: sifive: drop duplicated nodes and properties in sifive
riscv: dts: sifive: fix Unleashed board compatible
riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions