diff options
| author |   John Crispin <blogic@openwrt.org> | 2015-11-04 13:14:14 +0100 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2015-11-11 08:38:21 +0100 |
| commit | 26cfdbe30d81c209a5e81c4c311b02b10b5821c3 (patch) | |
| tree | 687a4201c886cc4113b0475be151799f5a737e4d /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | MIPS: lantiq: Return correct value for fpi clock on ar9 (diff) | |
| download | wireguard-linux-26cfdbe30d81c209a5e81c4c311b02b10b5821c3.tar.xz wireguard-linux-26cfdbe30d81c209a5e81c4c311b02b10b5821c3.zip | |
MIPS: lantiq: Initialize the USB core on boot
There is a DWC2 USB core in these SoCs. To make USB work we need to first
reset and power the state machine. These are SoC specific registers and
not part of the actual USB core.
Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11449/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions