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| author |   Andrey Gusakov <andrey.gusakov@cogentembedded.com> | 2021-09-30 00:34:32 +0300 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-10-15 09:46:14 +0200 |
| commit | 2bd9feed23166f5ab67dec2ca02bd3f74c77b0ba (patch) | |
| tree | 0caf91c073ccd8c26c4b1ffce206a66aa36652e1 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: r9a07g044: Add SDHI clock and reset entries (diff) | |
| download | wireguard-linux-2bd9feed23166f5ab67dec2ca02bd3f74c77b0ba.tar.xz wireguard-linux-2bd9feed23166f5ab67dec2ca02bd3f74c77b0ba.zip | |
clk: renesas: r8a779[56]x: Add MLP clocks
Add clocks for MLP modules on Renesas R-Car H3 and M3-W/N SoCs.
Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Link: https://lore.kernel.org/r/20210929213431.5275-1-nikita.yoush@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions