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author | 2018-04-17 13:48:11 +0530 | |
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committer | 2018-04-17 10:57:16 +0100 | |
commit | 2d045e94f3b4da9ac116adb7a7145b46861436ac (patch) | |
tree | 395fc09a8ba76570e8deea3f47a7b16ce19e437c /tools/perf/scripts/python/export-to-postgresql.py | |
parent | regulator: ab8500: Drop AB8540/9540 support (diff) | |
download | wireguard-linux-2d045e94f3b4da9ac116adb7a7145b46861436ac.tar.xz wireguard-linux-2d045e94f3b4da9ac116adb7a7145b46861436ac.zip |
regulator: lp87565: Add margin while populating ramp_delay
The slew rate might need a +/- 15% margin as per the latest data manual:
http://www.ti.com/lit/ds/snvsb22/snvsb22.pdf
Hence take a conservative approach to program 85% of the original
hardware slew rate so that the software accommodates the margin
delay while voltage switching. Hence reduce the default ramp_delay
populated in the descriptors also by 15%.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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