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| author |   Arnd Bergmann <arnd@arndb.de> | 2021-10-26 17:21:28 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2021-10-26 17:21:29 +0200 |
| commit | 2ec492731a1ff651d89c909ccce01fd69346d1f0 (patch) | |
| tree | 31fda164ff3bf1d13834ae01cac412cc499e6952 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: arm: Update ICST clock nodes 'reg' and node names (diff) | |
| parent | ARM: dts: at91: sama7g5-ek: use blocks 0 and 1 of TCB0 as cs and ce (diff) | |
| download | wireguard-linux-2ec492731a1ff651d89c909ccce01fd69346d1f0.tar.xz wireguard-linux-2ec492731a1ff651d89c909ccce01fd69346d1f0.zip | |
Merge tag 'at91-dt-5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt
AT91 DT #2 for 5.16:
- Add DT nodes for TCB and RTC blocks on SAMA7G5
- Add TCB0 for clocksource and clockevent functionality fallback only in
case PIT64B will fail to probe and as a testbed for this feature on
the Evaluation Kit.
* tag 'at91-dt-5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: dts: at91: sama7g5-ek: use blocks 0 and 1 of TCB0 as cs and ce
ARM: dts: at91: sama7g5: add tcb nodes
ARM: dts: at91: sama7g5: add rtc node
Link: https://lore.kernel.org/r/20211025163428.26285-1-nicolas.ferre@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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