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| author |   Arnd Bergmann <arnd@arndb.de> | 2025-03-19 21:45:35 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-03-19 21:45:36 +0100 |
| commit | 32e0c5fe6e8bfd31220f0b7921481f0e5fb6055b (patch) | |
| tree | e99a60b846cb5554e086686a993f5a83b7d7725c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge tag 'sunxi-dt-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt (diff) | |
| parent | dt-bindings: xilinx: Deprecate header with firmware constants (diff) | |
| download | wireguard-linux-32e0c5fe6e8bfd31220f0b7921481f0e5fb6055b.tar.xz wireguard-linux-32e0c5fe6e8bfd31220f0b7921481f0e5fb6055b.zip | |
Merge tag 'zynqmp-dt-for-6.14' of https://github.com/Xilinx/linux-xlnx into soc/dt
arm64: ZynqMP DT changes for 6.15
- Align clock nodes with DT binding
- Add the first VN-X Versal NET board
- Move constants out of DT bindings
* tag 'zynqmp-dt-for-6.14' of https://github.com/Xilinx/linux-xlnx:
dt-bindings: xilinx: Deprecate header with firmware constants
arm64: zynqmp: Use DT header for firmware constants
arm64: versal-net: Add description for b2197-00 revA board
dt-bindings: soc: Add new VN-X board description based on Versal NET
arm64: zynqmp: add clock-output-names property in clock nodes
Link: https://lore.kernel.org/r/CAHTX3d+u1VmxP4vm0peQS-ST7o0BuCpKUPRVCSLMfAAb=eV3Xg@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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