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author | 2021-05-06 19:19:24 +0300 | |
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committer | 2021-05-07 11:13:01 +0300 | |
commit | 33e7a975103cebb20e7dee743adc8f9335958139 (patch) | |
tree | 243681f3340ddffd156b316ea2d2cc9843927a1e /tools/perf/scripts/python/export-to-postgresql.py | |
parent | drm/i915/adl_p: ADL_P device info enabling (diff) | |
download | wireguard-linux-33e7a975103cebb20e7dee743adc8f9335958139.tar.xz wireguard-linux-33e7a975103cebb20e7dee743adc8f9335958139.zip |
drm/i915/xelpd: First stab at DPT support
Add support for DPT (display page table). DPT is a
slightly peculiar two level page table scheme used for
tiled scanout buffers (linear uses direct ggtt mapping
still). The plane surface address will point at a page
in the DPT which holds the PTEs for 512 actual pages.
Thus we require 1/512 of the ggttt address space
compared to a direct ggtt mapping.
We create a new DPT address space for each framebuffer and
track two vmas (one for the DPT, another for the ggtt).
TODO:
- Is the i915_address_space approaach sane?
- Maybe don't map the whole DPT to write the PTEs?
- Deal with remapping/rotation? Need to create a
separate DPT for each remapped/rotated plane I
guess. Or else we'd need to make the per-fb DPT
large enough to support potentially several
remapped/rotated vmas. How large should that be?
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Wilson Chris P <Chris.P.Wilson@intel.com>
Cc: Tang CQ <cq.tang@intel.com>
Cc: Auld Matthew <matthew.auld@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Wilson Chris P <Chris.P.Wilson@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210506161930.309688-5-imre.deak@intel.com
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