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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2018-07-11 13:14:44 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-08-27 17:00:18 +0200 |
| commit | 38c79e2899a66096583f3377c64b35f30584f1b4 (patch) | |
| tree | 7c8242b3318f184e721cb57cfdc6d6e5f5c05467 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: rcar-gen3: Rename rint to .r (diff) | |
| download | wireguard-linux-38c79e2899a66096583f3377c64b35f30584f1b4.tar.xz wireguard-linux-38c79e2899a66096583f3377c64b35f30584f1b4.zip | |
clk: renesas: rcar-gen3: Add support for OSC EXTAL predivider
Add a clock type and macro for defining clocks using the OSC EXTAL
predivider combined with a fixed divider.
On most R-Car Gen3 SoCs, the predivider value depends on mode pins, and
thus must be specified in the configuration structure.
Inspired by a patch in the BSP by Takeshi Kihara
<takeshi.kihara.df@renesas.com>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions