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| author |   Keerthy <j-keerthy@ti.com> | 2025-02-18 10:52:48 +0530 |
|---|---|---|
| committer |   Vignesh Raghavendra <vigneshr@ti.com> | 2025-03-02 18:43:33 +0530 |
| commit | 398898f9cca1a19a83184430c675562680e57c7b (patch) | |
| tree | 407a899f66e99ec6ad263d4676ed1cf8873f054d /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: ti: k3-am62p5-sk: Add boot phase tag for USB0 (diff) | |
| download | wireguard-linux-398898f9cca1a19a83184430c675562680e57c7b.tar.xz wireguard-linux-398898f9cca1a19a83184430c675562680e57c7b.zip | |
arm64: dts: ti: k3-j784s4-j742s2-main-common: Correct the GICD size
Currently we get the warning:
"GICv3: [Firmware Bug]: GICR region 0x0000000001900000 has
overlapping address"
As per TRM GICD is 64 KB. Fix it by correcting the size of GICD.
Cc: stable@vger.kernel.org
Fixes: 9cc161a4509c ("arm64: dts: ti: Refactor J784s4 SoC files to a common file")
Link: https://lore.kernel.org/r/20250218052248.4734-1-j-keerthy@ti.com
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions