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author | 2021-03-26 13:01:00 +0100 | |
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committer | 2021-05-11 09:57:06 +0200 | |
commit | 3a0e84845891eebccce767b4f8cd5ed1b9bffc14 (patch) | |
tree | 7d4a2b2c9b1fb524e8ef634b98df8a935a34cb73 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | clk: renesas: rcar-gen3: Add custom clock for PLLs (diff) | |
download | wireguard-linux-3a0e84845891eebccce767b4f8cd5ed1b9bffc14.tar.xz wireguard-linux-3a0e84845891eebccce767b4f8cd5ed1b9bffc14.zip |
clk: renesas: rcar-gen3: Add boost support to Z clocks
Add support for switching the Z and Z2 clocks between normal and boost
modes, by requesting clock rate changes to parent PLLs.
Inspired by a patch in the BSP by Takeshi Kihara
<takeshi.kihara.df@renesas.com>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210326120100.1577596-8-geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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