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| author |   Wolfram Sang <wsa+renesas@sang-engineering.com> | 2021-09-01 11:17:23 +0200 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-09-24 15:11:05 +0200 |
| commit | 3ae4087bf46a8772695a0441f1654eacddd3e2bb (patch) | |
| tree | 668dbb92fdb33f9141ab3c81b928a96695885ab1 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: rzg2l: Fix clk status function (diff) | |
| download | wireguard-linux-3ae4087bf46a8772695a0441f1654eacddd3e2bb.tar.xz wireguard-linux-3ae4087bf46a8772695a0441f1654eacddd3e2bb.zip | |
clk: renesas: r8a779a0: Add TPU clock
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210901091725.35610-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions