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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2020-07-13 10:33:35 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-07-13 10:33:35 +0200 |
| commit | 3c2543d39d061662230a3199c80522c0e91e0523 (patch) | |
| tree | 9cdcec74f13c495b73cabb292df8afe625d92cbc /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Linux 5.8-rc1 (diff) | |
| parent | clk: renesas: Add r8a774e1 CPG Core Clock Definitions (diff) | |
| download | wireguard-linux-3c2543d39d061662230a3199c80522c0e91e0523.tar.xz wireguard-linux-3c2543d39d061662230a3199c80522c0e91e0523.zip | |
Merge tag 'renesas-r8a774e1-dt-binding-defs-tag' into renesas-drivers-for-v5.9
Renesas RZ/G2H DT Binding Definitions
Clock and Power Domain definitions for the Renesas RZ/G2H (R8A774E1)
SoC, shared by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions