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| author |   Leilk Liu <leilk.liu@mediatek.com> | 2015-08-20 17:19:06 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2015-08-20 11:09:47 -0700 |
| commit | 44f636da4e71e0c73d6e29d0319a8954ce3f247a (patch) | |
| tree | 0218e366c0d4109e5ab92b4a94be75ea9bc2d5b7 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | spi: mediatek: remove redundant clock in prepare_hardware/unprepare_hardware (diff) | |
| download | wireguard-linux-44f636da4e71e0c73d6e29d0319a8954ce3f247a.tar.xz wireguard-linux-44f636da4e71e0c73d6e29d0319a8954ce3f247a.zip | |
spi: mediatek: fix spi incorrect endian usage
TX_ENDIAN/RX_ENDIAN bits define whether to reverse the endian
order of the data DMA from/to memory. The endian order should
keep the same with cpu endian.
Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions