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| author |   Pali Rohár <pali@kernel.org> | 2021-10-05 20:09:44 +0200 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2021-10-07 14:23:31 +0100 |
| commit | 46ef6090dbf590711cb12680b6eafde5fa21fe87 (patch) | |
| tree | 82bc70b546740ca29d614a7ca2c38bd6466b4c53 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | PCI: aardvark: Fix preserving PCI_EXP_RTCTL_CRSSVE flag on emulated bridge (diff) | |
| download | wireguard-linux-46ef6090dbf590711cb12680b6eafde5fa21fe87.tar.xz wireguard-linux-46ef6090dbf590711cb12680b6eafde5fa21fe87.zip | |
PCI: aardvark: Fix configuring Reference clock
Commit 366697018c9a ("PCI: aardvark: Add PHY support") introduced
configuration of PCIe Reference clock via PCIE_CORE_REF_CLK_REG register,
but did it incorrectly.
PCIe Reference clock differential pair is routed from system board to
endpoint card, so on CPU side it has output direction. Therefore it is
required to enable transmitting and disable receiving.
Default configuration according to Armada 3700 Functional Specifications is
enabled receiver part and disabled transmitter.
We need this change because otherwise PCIe Reference clock is configured to
some undefined state when differential pair is used for both transmitting
and receiving.
Fix this by disabling receiver part.
Link: https://lore.kernel.org/r/20211005180952.6812-6-kabel@kernel.org
Fixes: 366697018c9a ("PCI: aardvark: Add PHY support")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
Cc: stable@vger.kernel.org
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions