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| author |   Reza Amini <Reza.Amini@amd.com> | 2020-07-15 11:33:23 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-08-06 16:40:18 -0400 |
| commit | 471c1dd9546df81d259664ac3e2ab0e99169f755 (patch) | |
| tree | 9c7dfcbbaeedbe03a8cd923733a09745e289d774 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: Disable idle optimizations before programming DCN (diff) | |
| download | wireguard-linux-471c1dd9546df81d259664ac3e2ab0e99169f755.tar.xz wireguard-linux-471c1dd9546df81d259664ac3e2ab0e99169f755.zip | |
drm/amd/display: Allow asic specific FSFT timing optimization
[Why]
Each asic can optimize best based on its capabilities
[How]
Optimizing timing for a new pixel clock
Signed-off-by: Reza Amini <Reza.Amini@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions