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| author |   Imre Deak <imre.deak@intel.com> | 2020-07-21 02:29:52 +0300 |
|---|---|---|
| committer |   Jani Nikula <jani.nikula@intel.com> | 2020-08-19 15:23:43 +0300 |
| commit | 4a4064ad79699ee41b74c12fa4f9f960a5bf9b2d (patch) | |
| tree | 23e190981dd4c600d0b99bfd3b62bdcc53d585d1 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/selftests: Avoid passing a random 0 into ilog2 (diff) | |
| download | wireguard-linux-4a4064ad79699ee41b74c12fa4f9f960a5bf9b2d.tar.xz wireguard-linux-4a4064ad79699ee41b74c12fa4f9f960a5bf9b2d.zip | |
drm/i915/tgl: Make sure TC-cold is blocked before enabling TC AUX power wells
The dependency between power wells is determined by the ordering of the
power well list: when enabling the power wells for a domain, this
happens walking the power well list forward, while disabling them
happens in the reverse direction. Accordingly a power well on the list
must follow any other power well it depends on.
Since the TC AUX power wells depend on TC-cold being blocked, move the
TC-cold off power well before all AUX power wells.
Fixes: 3c02934b24e3 ("drm/i915/tc/tgl: Implement TC cold sequences")
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200720232952.16228-1-imre.deak@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
(cherry picked from commit b302a2e68807604af2a5015816c1d117747989b6)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions