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author | 2025-03-19 22:15:11 +0100 | |
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committer | 2025-03-19 22:15:12 +0100 | |
commit | 519df17cb03eb2408c3053d6052548c92d19c9b7 (patch) | |
tree | 3da7dcc8f32f30ac3af300dad0f19acc7f68f4ef /tools/perf/scripts/python/export-to-postgresql.py | |
parent | Merge tag 'omap-for-v6.15/dt-signed' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt (diff) | |
parent | riscv: dts: starfive: jh7110-pine64-star64: enable USB 3.0 port (diff) | |
download | wireguard-linux-519df17cb03eb2408c3053d6052548c92d19c9b7.tar.xz wireguard-linux-519df17cb03eb2408c3053d6052548c92d19c9b7.zip |
Merge tag 'riscv-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V Devicetrees for v6.15
Starfive:
All changes for jh7110-based boards including the removal of a dac
that does not exist and the addition of usb3 support on the star64 board
and pcie on the framework mainboard.
Microchip:
Update pcie reg properties to fix a mistake originally describing them.
Here rather than in fixes, since the driver maintains support for the
old format.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: starfive: jh7110-pine64-star64: enable USB 3.0 port
riscv: dts: starfive: jh7110: pciephy0 USB 3.0 configuration registers
riscv: dts: starfive: fml13v01: enable pcie1
riscv: dts: starfive: remove non-existent dac from jh7110
riscv: dts: starfive: Unify regulator naming scheme
riscv: dts: microchip: update pcie reg properties to new format
Link: https://lore.kernel.org/r/20250318-favorite-presuming-bf2fcf55bf6a@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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