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author | 2020-11-28 22:18:57 +0800 | |
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committer | 2020-11-30 11:18:29 +0000 | |
commit | 57e3cebd022fbc035dcf190ac789fd2ffc747f5b (patch) | |
tree | a566c7a05f60d395cc47e072fdd8e1d600bb535e /tools/perf/scripts/python/export-to-postgresql.py | |
parent | KVM: arm64: Remove unused __extended_idmap_trampoline() prototype (diff) | |
download | wireguard-linux-57e3cebd022fbc035dcf190ac789fd2ffc747f5b.tar.xz wireguard-linux-57e3cebd022fbc035dcf190ac789fd2ffc747f5b.zip |
KVM: arm64: Delay the polling of the GICR_VPENDBASER.Dirty bit
In order to reduce the impact of the VPT parsing happening on the GIC,
we can split the vcpu reseidency in two phases:
- programming GICR_VPENDBASER: this still happens in vcpu_load()
- checking for the VPT parsing to be complete: this can happen
on vcpu entry (in kvm_vgic_flush_hwstate())
This allows the GIC and the CPU to work in parallel, rewmoving some
of the entry overhead.
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Shenming Lu <lushenming@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20201128141857.983-3-lushenming@huawei.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions