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| author |   Johan Jonker <jbx6244@gmail.com> | 2020-11-18 14:58:16 +0100 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2020-11-29 20:10:44 +0100 |
| commit | 5868491e1257786628fdd2457dfb77609f49f91d (patch) | |
| tree | e5bfd293c079db123d47de750d07221e347f542a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: rockchip: Remove redundant null check before clk_prepare_enable (diff) | |
| download | wireguard-linux-5868491e1257786628fdd2457dfb77609f49f91d.tar.xz wireguard-linux-5868491e1257786628fdd2457dfb77609f49f91d.zip | |
clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks
Add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks,
so that the parent COMPOSITE_FRACMUX and COMPOSITE_NOMUX
also update.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20201118135822.9582-2-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions