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| author |   Swapnil Jakhade <sjakhade@cadence.com> | 2021-12-23 07:01:36 +0100 |
|---|---|---|
| committer |   Vinod Koul <vkoul@kernel.org> | 2021-12-27 16:35:09 +0530 |
| commit | 637feefb8ac53fbe1147edb707b03dc09839fdf5 (patch) | |
| tree | f0e0cd464a6687929a900c824d72f44517bf78ce /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration (diff) | |
| download | wireguard-linux-637feefb8ac53fbe1147edb707b03dc09839fdf5.tar.xz wireguard-linux-637feefb8ac53fbe1147edb707b03dc09839fdf5.zip | |
dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock
Add clock ID for Sierra derived reference clock.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211223060137.9252-15-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions