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| author |   Hyungwon Hwang <human.hwang@samsung.com> | 2015-06-15 13:03:17 +0900 |
|---|---|---|
| committer |   Kukjin Kim <kgene@kernel.org> | 2015-07-21 12:49:48 +0900 |
| commit | 65e3293381e1cf1abcfe1aa22b914650a40e3af4 (patch) | |
| tree | 75dbea674e76a3753cf7c37b8f1647d05c00f2b0 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Linux 4.2-rc1 (diff) | |
| download | wireguard-linux-65e3293381e1cf1abcfe1aa22b914650a40e3af4.tar.xz wireguard-linux-65e3293381e1cf1abcfe1aa22b914650a40e3af4.zip | |
ARM: dts: fix clock-frequency of display timing0 for exynos3250-rinato
After the commit abc0b1447d49 ("drm: Perform basic sanity checks on
probed modes"), proper clock-frequency becomes mandatory for
validating the mode of panel. The display does not work if there is
no mode validated. Also, this clock-frequency must be set
appropriately for getting required frame rate.
Fixes: abc0b1447d49 ("drm: Perform basic sanity checks on probed modes")
Cc: <stable@vger.kernel.org>
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Sigend-off-by: Kukjin Kim <kgene@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions