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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-05-04 11:03:00 +0200 |
|---|---|---|
| committer |   Rob Herring <robh@kernel.org> | 2021-05-04 09:05:46 -0500 |
| commit | 6799e3f281e962628be531e8331bacd05b866134 (patch) | |
| tree | 051433adcec504f1ac8256fd6f2c13a3325ac62c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dt-bindings: display: renesas,du: Add missing power-domains property (diff) | |
| download | wireguard-linux-6799e3f281e962628be531e8331bacd05b866134.tar.xz wireguard-linux-6799e3f281e962628be531e8331bacd05b866134.zip | |
dt-bindings: net: renesas,etheravb: Fix optional second clock name
If the optional "clock-names" property is present, but the optional TXC
reference clock is not, "make dtbs_check" complains:
ethernet@e6800000: clock-names: ['fck'] is too short
Fix this by declaring that a single clock name is valid.
While at it, drop the superfluous upper limit on the number of clocks,
as it is implied by the list of descriptions.
Fixes: 6f43735b6da64bd4 ("dt-bindings: net: renesas,etheravb: Add additional clocks")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/b3d91c9f70a15792ad19c87e4ea35fc876600fae.1620118901.git.geert+renesas@glider.be
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions