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| author |   Boerge Struempfel <boerge.struempfel@gmail.com> | 2023-05-30 16:16:38 +0200 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2023-05-30 15:20:09 +0100 |
| commit | 6a983ff5102ff0d859df05ca3f5cf2f6a17c0fad (patch) | |
| tree | ab1cb0d6f66f3272d565d1f555c64d50863a73e0 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | spi: add SPI_MOSI_IDLE_LOW mode bit (diff) | |
| download | wireguard-linux-6a983ff5102ff0d859df05ca3f5cf2f6a17c0fad.tar.xz wireguard-linux-6a983ff5102ff0d859df05ca3f5cf2f6a17c0fad.zip | |
spi: spi-imx: add support for SPI_MOSI_IDLE_LOW mode bit
By default, the spi-imx controller pulls the mosi line high, whenever it
is idle. This behaviour can be inverted per CS by setting the
corresponding DATA_CTL bit in the config register of the controller.
Also, since the controller mode-bits have to be touched anyways, the
SPI_CPOL and SPI_CPHA are replaced by the combined SPI_MODE_X_MASK flag.
Signed-off-by: Boerge Struempfel <boerge.struempfel@gmail.com>
Link: https://lore.kernel.org/r/20230530141641.1155691-3-boerge.struempfel@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions