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| author |   Jerome Brunet <jbrunet@baylibre.com> | 2018-01-19 16:42:36 +0100 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2018-02-12 09:49:23 +0100 |
| commit | 6c00e7b76021fcf4ddb64191ccdf62c722adf0d1 (patch) | |
| tree | 783c5d881ed9d73acbf63fb44eebc6bca9bd4b97 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: meson: axg: fix the od shift of the sys_pll (diff) | |
| download | wireguard-linux-6c00e7b76021fcf4ddb64191ccdf62c722adf0d1.tar.xz wireguard-linux-6c00e7b76021fcf4ddb64191ccdf62c722adf0d1.zip | |
clk: meson: add axg misc bit to the mpll driver
On axg, the rate of the mpll is stuck as if sdm value was 4 and could not
change (expect for mpll2 strangely). Looking at the vendor kernel, it
turns out a new magic bit from the undocumented HHI_PLL_TOP_MISC register
is required.
Setting this bit solves the problem and the mpll rates are back to normal
Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions