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| author |   Icenowy Zheng <icenowy@aosc.io> | 2019-07-28 11:12:27 +0800 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@bootlin.com> | 2019-08-23 09:14:48 +0200 |
| commit | 6f002c57c74616ab2bfd236f48bf254c30c5f36a (patch) | |
| tree | 84fa9d4bb09af3918b27381d65367493c0ecd740 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs (diff) | |
| download | wireguard-linux-6f002c57c74616ab2bfd236f48bf254c30c5f36a.tar.xz wireguard-linux-6f002c57c74616ab2bfd236f48bf254c30c5f36a.zip | |
ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3
Lichee zero plus is a core board made by Sipeed, which includes on-board
TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug
header, a microUSB slot and a gold finger connector for expansion. It
can use either Sochip S3 or Allwinner S3L SoC.
Add the basic device tree for the core board, w/o optional onboard
storage, and with S3 SoC.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions