diff options
| author |   Terry Zhou <bjzhou@marvell.com> | 2020-11-06 11:00:39 +0100 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2020-12-19 15:51:18 -0800 |
| commit | 6f37689cf6b38fff96de52e7f0d3e78f22803ba0 (patch) | |
| tree | 0242978f543481ee98806961a1ef2ed70d678225 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Linux 5.10-rc1 (diff) | |
| download | wireguard-linux-6f37689cf6b38fff96de52e7f0d3e78f22803ba0.tar.xz wireguard-linux-6f37689cf6b38fff96de52e7f0d3e78f22803ba0.zip | |
clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
There is an error in the current code that the XTAL MODE
pin was set to NB MPP1_31 which should be NB MPP1_9.
The latch register of NB MPP1_9 has different offset of 0x8.
Signed-off-by: Terry Zhou <bjzhou@marvell.com>
[pali: Fix pin name in commit message]
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 7ea8250406a6 ("clk: mvebu: Add the xtal clock for Armada 3700 SoC")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20201106100039.11385-1-pali@kernel.org
Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions