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| author |   Jerome Brunet <jbrunet@baylibre.com> | 2021-04-07 16:57:14 +0200 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2021-04-07 16:57:31 +0100 |
| commit | 6f68accaa8641b70b698da659216f82f87537869 (patch) | |
| tree | 44b5372808aa761a341d2868aee611a50ec94b77 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ASoC: tlv320aic32x4: Register clocks before registering component (diff) | |
| download | wireguard-linux-6f68accaa8641b70b698da659216f82f87537869.tar.xz wireguard-linux-6f68accaa8641b70b698da659216f82f87537869.zip | |
ASoC: meson: axg-frddr: set fifo depth according to the period
When the period is small, using all the FRDDR fifo depth increases the
latency of the playback because the following device won't start pulling
data until the fifo reaches the depth set. We can adjust this depth so trim
it down for small periods.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20210407145714.311138-1-jbrunet@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions