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| author |   Dilip Kota <eswara.kota@linux.intel.com> | 2020-07-17 14:27:55 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2020-07-22 01:55:58 +0100 |
| commit | 744cd0f212d72758fb094c1d13ec61b27ab6de3f (patch) | |
| tree | 4080eeaf67d863115ece41b17ab85a4bcddb68d6 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | spi: lantiq: Add fifo size bit mask in SoC specific data structure (diff) | |
| download | wireguard-linux-744cd0f212d72758fb094c1d13ec61b27ab6de3f.tar.xz wireguard-linux-744cd0f212d72758fb094c1d13ec61b27ab6de3f.zip | |
spi: lantiq: Move interrupt configuration to SoC specific data structure
Moving interrupt configuration to SoC specific data structure helps to add
support for newer SoCs on which SPI controller with lesser interrupt lines
compared to existing chipsets.
Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
Link: https://lore.kernel.org/r/7eb6d863515245fedfa0296c72082df107367d07.1594957019.git.eswara.kota@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions