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| author |   Marek Behún <kabel@kernel.org> | 2021-10-28 20:56:53 +0200 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2021-10-29 10:25:31 +0100 |
| commit | 7a41ae80bdcb17e14dd7d83239b8a0cf368f18be (patch) | |
| tree | 3b9c4d9144556f0574f11cc0c1e9dcfe62c46b06 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | PCI: aardvark: Fix reporting Data Link Layer Link Active (diff) | |
| download | wireguard-linux-7a41ae80bdcb17e14dd7d83239b8a0cf368f18be.tar.xz wireguard-linux-7a41ae80bdcb17e14dd7d83239b8a0cf368f18be.zip | |
PCI: pci-bridge-emul: Fix emulation of W1C bits
The pci_bridge_emul_conf_write() function correctly clears W1C bits in
cfgspace cache, but it does not inform the underlying implementation
about the clear request: the .write_op() method is given the value with
these bits cleared.
This is wrong if the .write_op() needs to know which bits were requested
to be cleared.
Fix the value to be passed into the .write_op() method to have requested
W1C bits set, so that it can clear them.
Both pci-bridge-emul users (mvebu and aardvark) are compatible with this
change.
Link: https://lore.kernel.org/r/20211028185659.20329-2-kabel@kernel.org
Fixes: 23a5fba4d941 ("PCI: Introduce PCI bridge emulated config space common logic")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
Cc: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions