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| author |   Stephen Boyd <sboyd@kernel.org> | 2020-06-23 12:12:43 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-06-23 12:12:43 -0700 |
| commit | 7aae3c161e0677018d6b3be2b79c4dbbedda9091 (patch) | |
| tree | 745675d5eaa699b998063f810a6f1f587aed33d2 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge branch 'clk-qcom' into clk-next (diff) | |
| parent | clk: vc5: Enable addition output configurations of the Versaclock (diff) | |
| download | wireguard-linux-7aae3c161e0677018d6b3be2b79c4dbbedda9091.tar.xz wireguard-linux-7aae3c161e0677018d6b3be2b79c4dbbedda9091.zip | |
Merge branch 'clk-vc5' into clk-next
* clk-vc5:
clk: vc5: Enable addition output configurations of the Versaclock
dt: Add additional option bindings for IDT VersaClock
clk: vc5: Allow Versaclock driver to support multiple instances
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions